https://wafernote.pages.dev/How chips are made, and what people mix up about them.en-usFri, 21 Aug 2026 21:14:35 +0000https://wafernote.pages.dev/posts/why-yield-is-not-the-same-as-utilization/Thu, 20 Aug 2026 09:00:00 -0400https://wafernote.pages.dev/posts/why-yield-is-not-the-same-as-utilization/Yield is how much of the product is good. Utilization is how much of the plant or tool is busy. Both are percentages. They are not the same meter.https://wafernote.pages.dev/posts/what-actually-happens-at-a-wafer-probe/Wed, 19 Aug 2026 09:00:00 -0400https://wafernote.pages.dev/posts/what-actually-happens-at-a-wafer-probe/Probe is electrical sort on the intact wafer. Needles or microsprings touch pads, the tester scores each die, and the wafer is mapped before it is cut.https://wafernote.pages.dev/posts/why-a-nanometer-node-is-not-a-transistor-size/Tue, 18 Aug 2026 09:00:00 -0400https://wafernote.pages.dev/posts/why-a-nanometer-node-is-not-a-transistor-size/A foundry node is a generation label. It is not the width of a transistor and not the length of a gate.