What actually happens at a wafer probe

Wafer probe is electrical test of the dies while they are still on the intact wafer. A probe card presents a field of needles or microsprings to the bond pads or bumps. A tester runs a program. Each die is scored, the wafer is mapped, and only then does the lot move toward dicing and assembly.

The station looks like a microscope on a granite slab because that is what it is: a precision aligner with a vacuum chuck. The wafer sits on the chuck. The card hangs above it. Software walks the stepping grid so every die — or every sampled die — gets a touchdown. Nothing about that motion is packaging. The silicon is still one disk.

The card is the custom part. A production card is a printed circuit or a ceramic plate with a dense forest of tips, each aimed at a pad or a bump. The tips are short on purpose. They have to land, wipe a little, and leave a mark the next step can live with. A bent tip, a dirty pad, or a wrong overtravel shows up as a false fail or a damaged pad. That is why probe is both a test step and a mechanical step.

What the tester asks depends on the product. A parametric insert might measure leakage, threshold, or a monitor structure in the scribe. A functional insert might boot a built-in self-test, scan a block, or run a memory march. High-volume logic often does a reduced pattern set at probe and saves the long suite for package test, because time on a probe cell is expensive and the wafer is still whole.

The chuck can be cold, hot, or both. Some lots see more than one temperature pass. Some products see a fuse or trim step in the same visit: measure, blow, measure again. Probe is not only a gate. It is sometimes the last place you can adjust a die before the wafer is cut.

The output that matters to the next boat is the wafer map. Each site gets a bin: good enough for the main product, good enough for a slower bin, reject, or “do not pick.” Ink dots used to mark the bad ones. Most lines now keep an electronic map and let the dicing or pick tool read it. The map is how a bad die is kept out of a good package without anyone staring at every chip.

People mix probe with final test because both use a tester and both produce a yield number. Probe is still on the wafer. Final test is usually after the die is in a package, with different access, different thermals, and a different program. A die can pass probe and fail later. A die can also be rejected at probe for a pad issue that would never have shown up in a socket.

The racks beside the station are not decoration. They hold the automatic test equipment: channels, power supplies, and the computer that runs the program. Cables to the probe card are short on purpose. Every extra inch is inductance and a chance to fail a timing check that the silicon would have passed. When a cell is down, it is often a card, a cable, or a dock, not a mystery in the process recipe.

Sort is the name for the decision, not for the needles. After the map is closed, someone — or a rule — decides which bins ship to assembly. A colored grid on a wafer, or a file that looks like one, is the record of that decision. It is not a process defect map from a scan tool, and it is not a utilization chart from the dispatcher. It is a list of sites and scores.

If you are standing on a tour and someone says “we test the wafer here,” ask three questions. What is touching the pads? What program is running? What map leaves with the lot? Those three answers are wafer probe. Everything else — package test, system test, a burn-in rack — is a later station with a later job.