Halo Wafer Note

Process

Why a nanometer node is not a transistor size

Halo

A nanometer node is a product name, not a ruler reading. When a foundry says “3 nanometer,” it is not claiming that each transistor is three nanometers wide, and it is not claiming that the gate is three nanometers long. The integer is a generation label for a bundle of density, speed, and power.

For a long stretch the number in the node name tracked something you could measure on the wafer. Early CMOS generations used half the metal pitch, or a drawn gate length, as the public handle. That coupling did not survive the last several shrinks. Vendors still needed a way to say this family is denser and faster than the last one, without agreeing on one shared geometric standard. The node name became a commercial label.

That is why two “7 nanometer” products can disagree on the distances that actually sit in silicon. One shop’s contacted poly pitch can be looser than another’s. Minimum metal pitch can differ by layer and by product. An SRAM bit cell can be smaller on the part that looks, on a slide, like the older name. Comparing the brochure integers is like comparing two machine shops because both stamped “fine” on the crate.

What you can measure is more boring and more useful. Contacted poly pitch is the repeat distance of the transistor gate along the cell. Metal pitch is the repeat distance of a given interconnect layer. Fin pitch, or the stack height of a nanosheet device, describes the body of the transistor. None of those numbers is required to match the marketing node. A lithography reticle still carries the real drawn shapes. The node name does not have to appear anywhere on that glass.

People reach for the nanometer anyway because the unit is real. Gates, spacers, and lines are measured in nanometers. Putting a real unit on a brand name makes the brand feel like a dimension. Headlines then treat the next node as a shrink factor — half the size, twice the count — which is not what the label promises. A new node can buy performance with a new device, a new middle-of-line scheme, or a new library, not only with a smaller pitch.

The wafer itself does not announce the node. Oxide color, notch, and polish tell you that you are looking at silicon. They do not tell you whether the lot is a “5” or a “3.” That number lives in the traveler, the process of record, and the press slide. Confusing the wafer you can hold with the label on the slide is the same error as confusing a city name with a street width.

Designers feel the gap in the library. A standard-cell track height, a contacted poly pitch, and a minimum metal pitch set how tightly you can pack logic. Those are the knobs that change congestion and power. The node name is the folder those knobs arrived in. If you are estimating die size, you need the pitches and the cell height, not the integer in the announcement.

Lithography adds another split. Extreme ultraviolet scanners print a tighter pitch than the deep-ultraviolet tools they replaced on critical layers, but a node is not “the wavelength.” Multi-patterning on older tools can still land a pitch that a casual reader would file under a smaller name. The chamber you see on a tour is a printer. The node is the product family that printer is serving this year.

Interconnect is the third split. After the device is built, copper lines and vias carry the signals. Those lines have their own pitches, their own resistance, and their own limits. A transistor can be small while the wiring still dominates delay. Calling the whole stack by one nanometer figure hides that stack. A microscope view of metal is a map of wiring, not a proof of the brochure number.

If you need a physical comparison, ask for contacted poly pitch, a published minimum metal pitch, and a density figure such as SRAM cell size or transistors per square millimeter. Those are still marketing-adjacent, and they still vary by product, but they point at geometry instead of a generation nickname.

Read a node name as a generation label. Read a pitch as a size. When someone says a chip is “3 nanometer,” ask which pitch they mean — and whether they mean a pitch at all.